A conventional semiconductor device is provided with various types of circuit elements forming circuits and wirings interconnecting the circuit elements on a silicon substrate, for example. Those wirings usually are formed in a multi-level structure. On an uppermost wiring layer, electrodes for external connections (which is defined as a pad hereinafter), and repair fuses for replacing a defective circuit with a redundant circuit are formed.
FIG. 6 is a sectional view schematically showing the uppermost wiring layer of a conventional semiconductor device. In FIG. 6, a fuse 3a, a wiring 3b, and a pad 3c are formed on an interlayer insulator 1, as the uppermost wiring layer 3. Under the interlayer insulator 1, there is a semiconductor substrate, on which other wiring layers and circuit elements such as transistor are formed.
As shown in FIG. 6, on the uppermost wiring layer 3 formed by etching a metal such as an aluminum alloy, a passivation film 5 made of dense silicon nitride film is formed by Chemical Vapor Deposition process (CVD) in order to prevent a mechanical breakdown and penetration of moisture or impurities such as sodium ion that causes failure of the semiconductor device.
An opening 7 for exposing a part of a surface of the pad 3c is formed by etching on the passivation film 5. The passivation film 5 on the fuse 3a is also etched to form an opening 6 in need of carrying out the following cutting process, resulting that the thickness of the passivation film 5 becomes thinner than the other portions. For instance, while the passivation film 5 is approximately 1000 nm in thickness, the film thickness at the opening 6 is approximately 150 nm.
The fuse 3a, as well as the wiring 3b, consists of a metal like the aluminum alloy. The necessity of the fuse cutting is decided according to an analysis of electrical characteristics test through the pad 3c. If the fuse cutting is required, the fuse 3a is heated by irradiation of a laser or a charged beam (an ion beam, for example) through the thin passivation film 5, and then the fuse 3a is blown and cut by liquefying and evaporating. According to this process, the defective circuit is turned out to be replaced with the redundant circuit.
Even if the fuse 3a is in the state of being coated by the thick passivation film 5 as well as the other portions, the cutting process of the fuse 3a can be carried out. In such case, since the cutting process will cause damages to the other portions other than the fuse 3a, the amount of irradiation energy of the laser cannot be increased needlessly. That is, when the fuse cutting is carried out on the fuse 3a coated by the thick passivation film 5, the processing time increases depending on the thickness of the passivation film 5. Therefore, by letting passivation film 5 thinner on the fuse 3a as mentioned above, the cutting process of the fuse 3a can be easily carried out and the penetration of moisture or impurities into non-cutting fuses 3a is prevented.
In case of the semiconductor device for the BGA Package (Flip Chip Bonding), a bump is formed on the passivation film 5 illustrated in FIG. 6 in a following way. As shown in FIG. 7, a surface insulating film 31 made of BCB (benzocycrobuten), which is for the planarization and the surface protection, is formed on the passivation film 5. An opening for exposing a part of the surface of the pad 3c is formed through the surface insulating film 31.
On a surface and a periphery of the opening, a barrier metal layer 32 made of such as nickel is formed in order to improve the adhesion between a bump material (solder) filling the opening by subsequent steps and the surface insulating film 31, and also to prevent the bump material from diffusing to the surface insulating film 31.
Next, on an upper surface of the insulating film 31, a metal mask having an opening in bump formation position that corresponds to the barrier metal layer 32, is placed, and a solder paste is patterned through the metal mask. After the patterned solder paste is reflowed, a spherical solder bump 33 is formed by the action of the surface tension.
In the semiconductor device for the BGA package, as the number of pins are increased and each pin pitch is reduced, the respective gaps between wirings 3b, forming the uppermost wiring layer 3, become narrow, as shown in FIG. 7. Accordingly, at such region of wirings 3b being in close, the passivation film 5 has excessive uneven structure due to the uneven structure of wirings 3b. Additionally, in the process of forming the passivation film 5 in such region, the film material on the wirings 3b has been connected before the gaps between the wirings 3b are completely filled, whereby a void 41 being not filled with the passivation film 5 is formed between the wirings 3b. 
Moreover, in the semiconductor device for the BGA package, the thick surface insulating film 31 is formed on the passivation film 5, as shown in FIG. 7. This structure makes it easy to generate a large stress by the heating in forming the solder bump 33. Consequently, when the stresses are concentrated on the uneven structure of the passivation film 5 and the voids 41 are existed therein, cracks 42 will appear in the passivation film 5 and the interlayer insulator 1.
As a solution, in the semiconductor device for the BGA package, a structure as shown in FIG. 8A is adopted in order to avoid the voids 41 being formed. In the structure that is disclosed in Kohyo (National Publication of Translated Version) No. 2002-500440, the passivation film 5 is formed in a two-layer structure including a first insulating film 11 and a second insulating film 12. The first insulating film 11 has a high filling capability for the gaps between the wirings 3b, and is superior in planarization of a surface of a generated film, like a silicon dioxide film deposited by CVD process using source gas including Silane (e.g. SiH4 and O2 mixture), for example. The second insulting film 12 consists of silicon nitride film placed on the first insulting film 11 that prevents moisture or impurities penetrating into the first insulating film 11.
Since the passivation film is formed in such two-layer structure wherein the first insulating film 11 with the high filling capability is placed under the second insulating film 12, the generation of voids 41 can be prevented, and the uneven structure of the passivation film also can be improved significantly. In result, it is possible to mitigate the stress concentration and avoid the occurrence of cracks 42.